Paper Title
Implementation Of Viterbi Decoder On FPGA To Improve Design
Abstract
In the data transmissions over wireless channels are affect by attenuation, distortion, interference and noise,
which affects the receiver’s ability to receive correct information. Convolution coding with Viterbi decoding is a FEC
technique that is particularly suited to a channel in which transmitted signal is corrupted mainly by additive white Gaussian
noise (AWGN).Convolutional codes are used for error correction. They have rather good correcting capability and perform
well even on very bad channels with error probabilities. Viterbi decoding is the best technique for decoding the Convolutional
codes but it is limited to smaller constraint lengths. Viterbi algorithm is a well-known maximum-likelihood algorithm for
decoding of convolutional codes. In this paper, we present a implementation of Viterbi decoder on Fpga to improve design
with a constraint length of 7 and a code rate of 1/2.We also use Trace back Implementation of survivor sequence memory
management for low power decoder design.