Paper Title
Swift And Approximate Multiply And Accumulate Unit For Embedded DSP Applications: A Review
Abstract
At present era energy consumption in every portable and embedded device is main issue. As we know processor
is part of portable and embedded device and multiplier unit is important part of processor. So this paper presents the FPGA
comparison, delay and frequency analysis of proposed approximate MAC Unit. The MAC unit is a 8x8-bit Uradhav
multiplier with a 16-bit accumulator. The paper’s main focus was to analyze fast adder algorithms and multiplication
schemes, and utilizes them in the design and implementation of a MAC unit. Major important issue in digital circuits besides
speed, area, power consumption is accuracy. In this work, our main focus is on performance and accuracy, but we do provide
some numbers for the arithmetic units relating to energy and power. This is to provide an estimate of the amount of energy
and power consumed by the units we choose to implement. The priorities of this paper in order of importance, are, Robust
and safe circuits, Design time, Area/speed balance. Using Vedic mathematics and approximation a new multiplier technique
is proposed which reduces the delay and hardware complexity. Here a new approximate Multiplier technique is proposed
whose the lsb four bits are approximated. The proposed approximate and Accurate multiplier and adder and Multiply and
accumulate unit are designed on Xilnx FPGA Virtex 6 device and analyzed the results. The proposed MAC Unit provides an
accuracy of . The overall area and Delay and Frequency analysis are presented and compared. From the results we can depict
that up to 35% of reduction at all levels are achieved.
Keywords- Vedic Mathematics, Urdhva Tiryakbhyam, Multiplication, Approximation, Ripple Carry Adder, Carry-Look-
Ahead Adder, Verilog HDL Simulation, MAC Unit