Paper Title
Design Of An Area Efficient And Low Power Composite S-Box With Complexity Reduced Multiplicative Inverse Unit

Abstract
Abstract: Advanced Encryption Standard is the most important technique for reliable data transmission in the field of satellite communication, ATM, Net Banking, and E-Commerce etc. Currently several secure transmission techniques are established for Specific purposes. However, there is trade-off between chip size reduction and high security. S-box is the heart of the AES technique. Previously, AES S-box has been designed using Linearity or Non-linearity technique. It uses Look up Table (LUT) to store the corresponding Substitution value for a given input. Therefore, it consumes more area and power with low security. To overcome this problem, the 8 bit Composite S-box is used with Galois Field GF (24)2. Composite S-box unit consists of Inverse affine/affine matrix, Isomorphic mapping, and Multiplexer and Multiplicative inverse units. Isomorphic and inverse Isomorphic mapping is used to convert GF (28) into GF (22^2) and vice versa respectively during encryption and decryption process. However, the multiplicative Inverse unit is the fundamental unit of composite S-box. In this paper, the design of complexity reduced multiplicative inverse for GF (24) structure is presented and incorporated into composite S-box for AES. The proposed Multiplicative inverse unit in Composite S-box consists only less number of gates than existing Multiplicative inverse unit. Hence, the proposed composite S-box with reduced multiplicative inverse based AES offers low area, power and high security than the conventional AES with regular multiplicative inverse based composite S-box. Keywords: Linearity S-box, Non-Linearity S-box, Composite S-box, Complexity reduced Multiplicative Inverse, Isomorphic mapping and FPGA.

Author - K. Sandyarani, P.Nirmal Kumar

Published : Volume-2, Issue-8  ( Aug, 2015 )

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